SOI Wafer Applications & Manufacturing Process

SOI Applications: Ultra flat SOI wafer

• Low stress 501 wafer
• Small quantity available
• Customized layer doping and thickness
• Fast turn around
• High-speed High-temperature ICs
• Low-power Low-voltage ICs
• Microwave coin opponents Power device

Standard specifications: Diameter 4" 6" 8"Device layer2 um 300 um Thickness tolerance-FI-0.5 um +1-2 um Conductivity type P- type or N- type Orientation, Resistivity range0.001 - 10000 ohm-cm Buried oxide layer 500 A - 4 um Thickness tolerance+I-5 %Handle wafer>. 300 urn

Used in neural probes applied watt:

Step 1 utilizes an available Applied Watts SOI wafer that has a Standard Device Layer of 25-m, a Buried Oxide Layer of 1-m, and a Base Silicon Layer of 550-m. This wafer is available in quantities of (25), (50) or more.

Step 2 deposits a 0.5-m layer of Silicon Nitride using AVV available LPCVD process, which is a low-pressure chemical vapor deposition.

Step 3 etches the holes utilizing a Reactive Ion Etch (RIE), a wet etch process that takes approximately 30 minutes.

Step 4 is an oxide deposition using LPCVD closing some holes and leaving channels for the electrodes not shown in this illustration.

APPLICATION SUCCESS:

The end result was a successful micro fabrication process that utilized the SOI technology requiring only RIE to define the outline of the device. Signals were able to be captured with the customer's final product and used for the addition of on-board electronics. The additions of 6 mm long by 70-m wide pins were used primarily for sensory input.

GRAPHENE PRODUCTION UTILIZING SILICON WAFERS:

Commercial graphene production utilizes silicon wafers as a base substrate. This technique grows a high-quality graphene (single-crystal) on silicon wafers, which is then appropriate for use in transistors with ultra-low power consumption. The lower power increases processing clock speeds by two fold and reduces heat leading to a higher gigahertz spec, potentially up to 100.

MANUFACTURING PROCESS:

Step 1 involves coating the wafer in a layer of germanium (Ge), and then gently dipping the wafer into a solution of hydrofluoric (HF) acid stripping off the germanium oxide and leaving a multitude of hydrogen atoms, which bond to the germanium.

Step 2 involves a chemical vapor deposition (CVD) process that deposits the graphene layer on top of what is now an H-terminated germanium.

Step 3; the wafer is baked and cooled under vacuum to prepare it for the graphene to be peeled off of the silicon wafer. The graphene monolayer crystals give the peeled layer a crease-free high quality sheet to be placed on your substrate.

The graphene sheets switching capability at low voltages (less than 0.5volts) has the potential to solve one of the greatest challenges in electronics. Tunnel transistors, enabling supply voltage scaling, would be able to filter through the energy barrier instead of jumping through.